`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2022/04/18 00:29:50
// Design Name: 
// Module Name: slave
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module slave
#(parameter N=0)
(
AXI4_Lite.Slave s_axilite
    );
logic [31:0] RAM [0:255];            //RAM模型
logic [31:0] wr_addr;
logic [31:0] rd_addr;                //读写地址锁存
//RAM
initial
begin
   for(int i=0;i<256;i++)
       RAM[i]=0;
end
//bresp
assign s_axilite.bresp=2'b00;         //always OKEY
//awaddr
always_ff@(posedge s_axilite.aclk)
if(s_axilite.awvalid&&s_axilite.awready)
    wr_addr<=s_axilite.awaddr[31:2];                  //转化为字地址
//awready
always_ff@(posedge s_axilite.aclk,negedge s_axilite.aresetn)
if(~s_axilite.aresetn)
    s_axilite.awready<=0;
else if(s_axilite.awvalid&&~s_axilite.awready)
    s_axilite.awready<=1;
else if(s_axilite.awvalid&&s_axilite.awready)
begin
    s_axilite.awready<=0;
	$display("$time=%p,slave %d address channel handshake finished",$time,N);
end
//wready
always_ff@(posedge s_axilite.aclk,negedge s_axilite.aresetn)
if(~s_axilite.aresetn)
    s_axilite.wready<=0;
else if(s_axilite.wvalid&&~s_axilite.wready)
    s_axilite.wready<=1;
else if(s_axilite.wvalid&&s_axilite.wready)
begin
    s_axilite.wready<=0;
	$display("$time=%p,slave %d data channel handshake finished",$time,N);
end
//wdata
always_ff@(posedge s_axilite.aclk)
if(s_axilite.wvalid&&s_axilite.wready)
    RAM[wr_addr]<=s_axilite.wdata;
//bvalid
always_ff@(posedge s_axilite.aclk,negedge s_axilite.aresetn)
if(~s_axilite.aresetn)
   s_axilite.bvalid<=0;
else if(s_axilite.wvalid&&s_axilite.wready)
   s_axilite.bvalid<=1;
else if(s_axilite.bvalid&&s_axilite.bready)
begin
   s_axilite.bvalid<=0;
   $display("$time=%p,slave %d response channel handshake finished",$time,N);
end
//***********************************************************************deal with read
//arready
always@(posedge s_axilite.aclk,negedge s_axilite.aresetn)
if(~s_axilite.aresetn)
   s_axilite.arready<=0;
else if(s_axilite.arvalid&&~s_axilite.arready)
   s_axilite.arready<=1;
else if(s_axilite.arready&&s_axilite.arvalid)
   s_axilite.arready<=0;
//rd_addr
always@(posedge s_axilite.aclk)
if(s_axilite.arvalid&&s_axilite.arready)
   rd_addr<=s_axilite.araddr[31:2];
//rdata
always@(*)
if(s_axilite.rvalid)
   s_axilite.rdata=RAM[rd_addr];
else
   s_axilite.rdata=0;
//rresp
assign s_axilite.rresp=2'b00;
//rvalid
always@(posedge s_axilite.aclk,negedge s_axilite.aresetn)
if(~s_axilite.aresetn)
   s_axilite.rvalid<=0;
else if(s_axilite.arvalid&&s_axilite.arready)
   s_axilite.rvalid<=1;
else if(s_axilite.rvalid&&s_axilite.rready)
   s_axilite.rvalid<=0;

endmodule
